Field of the Invention
The present invention generally relates to high-speed data communication, and more particularly, to equalization techniques for high-speed data communication.
Description of the Related Art
In a data communication network, data signals are exchanged between transmitters and receivers at varied transmission rates over transmission channels. With advancement in data communication networks, there is a need for high transmission rates of data signals. However, a data signal transmitted at a high transmission rate is subject to distortion. The data signal may be distorted either by inter-symbol interference (ISI), random noise, or crosstalk. At the receiver, it is difficult to recover the original data bits from the distorted data signal.
A known solution in the art is the use of channel equalizers in the receivers to eliminate the distortion in received data signals. Channel equalizers are either linear or non-linear equalizers. A linear equalizer minimizes the distortion between received and transmitted data signals. However, when the channel distortion is too severe, the linear equalizer tends to enhance the noise in the received data signals. A non-linear equalizer is employed to eliminate distortion in the received data signals for channels with severe channel distortion. An example of a non-linear equalizer is a decision feedback equalizer (DFE), which eliminates the distortion in the received data signals without amplifying noise and crosstalk. The DFE calculates an error, based on the previous bits of the distorted data signal, and subtracts the error from the current bit of the distorted data signal.
The DFE includes summer circuits, decision-making slicer circuits, and a feedback circuit. A summer circuit adds feedback signals to the received data signal. A decision-making slicer circuit samples the received data signal to detect logic levels of data bits in the received data signal and output corresponding binary values. A feedback circuit includes feedback generators, which generate weight coefficients that are multiplied with the previously detected data bits and are fed back to the summer circuit as feedback signals. The weight coefficients are referred to as “taps” and are represented by h1, h2, and so on. For an M-tap DFE, the taps are represented by h1, h2, and so on, till hm. The number of taps required in the DFE increases with an increase in data signal distortion.
The timing paths of the DFE are represented by a unit interval (UI), i.e., a predetermined time interval. The period available for correction of errors in the received data signals is referred to as a “fundamental timing limit” of the DFE. The clock-to-output delays, propagation delays, and set-up times of the summer circuits, the decision-making slicer circuits, and the feedback circuits govern the fundamental timing limit of the DFE. The h1 tap corrects the error in a data bit that arrives at the DFE one UI earlier than a current data bit. The h2 tap corrects the error in a data bit that arrives at the DFE two UIs earlier than the current data bit.
The DFE implemented in a full-rate clock architecture has a fundamental timing limit of one UI. Thus, in the full-rate clock architecture, the propagation delay and the setup time in summer, the decision-making slicer, and the feedback circuits constitute less than one UI. Further, the DFE that is implemented in a half-rate clock architecture has a fundamental timing limit of one UI. However, the DFE that is implemented in the half-rate clock architecture with a technique “loop unrolling” has the fundamental timing limit of two UI.
FIG. 1A shows a conventional DFE 100 for compensating an error in an analog input signal received thereby. The DFE 100 is implemented in a half-rate architecture. The DFE 100 includes first through sixth summer circuits 102a-102f, first through tenth latches 104a-104j, first and second multiplexers 106a and 106b, and first and second feedback generators 108a and 108b. The first through fourth latches 104a-104d and the fifth through eighth latches 104e-104h are referred to as master latches 104a-104d and slave latches 104e-104h, respectively.
The first summer circuit 102a receives the analog input signal and a first weighted feedback signal, and generates a first intermediate signal. The second summer circuit 102b receives the analog input signal and a second weighted feedback signal, and generates a second intermediate signal. The third summer circuit 102c is connected to the first summer circuit 102a for receiving the first intermediate signal and a first offset voltage value, and generating a third intermediate signal. The fourth summer circuit 102d is connected to the first summer circuit 102a for receiving the first intermediate signal and a second offset voltage value, and generating a fourth intermediate signal.
The fifth summer circuit 102e is connected to the second summer circuit 102b for receiving the second intermediate signal and the first offset voltage value, and generating a fifth intermediate signal. The sixth summer circuit 102f is connected to the second summer circuit 102b for receiving the second intermediate signal and the second offset voltage value, and generating a sixth intermediate signal. The first and second offset voltage values are predetermined voltage values added to the first and second intermediate signals. The first and second offset voltage values have the same voltage values, but opposite polarities. The technique of adding such predetermined voltage values to the first and second intermediate signals is referred to as loop unrolling. Implementation of the loop unrolling technique eliminates the settling time required by first and second weighted feedback signals.
The first latch 104a has an input terminal connected to the third summer circuit 102c for receiving the third intermediate signal, a clock input terminal for receiving a first clock signal, and an output terminal for outputting a first compensated signal. The second latch 104b has an input terminal connected to the fourth summer circuit 102d for receiving the fourth intermediate signal, a clock input terminal for receiving the first clock signal, and an output terminal for outputting a second compensated signal. The third latch 104c has an input terminal connected to the fifth summer circuit 102e for receiving the fifth intermediate signal, a clock input terminal for receiving a second clock signal, and an output terminal for outputting a third compensated signal. The fourth latch 104d has an input terminal connected to the sixth summer circuit 102f for receiving the sixth intermediate signal, a clock input terminal for receiving the second clock signal, and an output terminal for outputting a fourth compensated signal.
The fifth latch 104e has an input terminal connected to the output terminal of the first latch 104a for receiving the first compensated signal, a clock input terminal for receiving the second clock signal, and an output terminal for outputting a delayed first compensated signal. The sixth latch 104f has an input terminal connected to the output terminal of the second latch 104b for receiving the second compensated signal, a clock input terminal for receiving the second clock signal, and an output terminal for outputting a delayed second compensated signal.
The first multiplexer 106a has first and second input terminals connected to the output terminals of the fifth and sixth latches 104e, and 104f for receiving the delayed first and second compensated signals, respectively, a select terminal for receiving a first select signal, and an output terminal for outputting a first feedback signal. The ninth latch 104i has an input terminal connected to the output terminal of the first multiplexer 106a for receiving the first feedback signal, a clock input terminal for receiving the second clock signal, and an output terminal for outputting a delayed first feedback signal. The first feedback generator 108a has an input terminal connected to the output terminal of the ninth latch 104i for receiving the delayed first feedback signal, multiplying the delayed first feedback signal with a third offset voltage value, and an output terminal for generating the first weighted feedback signal. The output terminal of the first feedback generator 108a is connected to the first summer circuit 102a. Thus, the first weighted feedback signal compensates the error in the analog input signal received at the first summer circuit.
The seventh latch 104g has an input terminal connected to the output terminal of the third latch 104c for receiving the third compensated signal, a clock input terminal for receiving the first clock signal, and an output terminal for outputting a delayed third compensated signal. The eighth latch 104h has an input terminal connected to the output terminal of the fourth latch 104d for receiving the fourth compensated signal, a clock input terminal for receiving the first clock signal, and an output terminal for outputting a delayed fourth compensated signal.
The second multiplexer 106b has first and second input terminals connected to the output terminals of the seventh and eighth latches 104g and 104h for receiving the delayed third and fourth compensated signals, respectively, a select terminal connected to the output terminal of the ninth latch 104i for receiving the delayed first feedback signal as a second select signal, and an output terminal for outputting a second feedback signal. The tenth latch 104j has an input terminal connected to the output terminal of the second multiplexer 106b for receiving the second feedback signal, a clock input terminal for receiving the first clock signal, and an output terminal for outputting the delayed second feedback signal. The first multiplexer 106a receives the delayed second feedback signal as the first select signal. The second feedback generator 108b has an input terminal connected to the output terminal of the tenth latch 104j for receiving the delayed second feedback signal, multiplying the delayed second feedback signal with the third offset voltage value, and an output terminal for generating the second weighted feedback signal. The output terminal of the second feedback generator 108b is connected to the second summer circuit 102b. Thus, the second weighted feedback signal compensates the error in the analog input signal. The first and second clock signals have a predetermined phase difference of 180 degrees between them. Thus, the second clock signal is an inverted first clock signal.
Referring to FIG. 1B with continued reference to FIG. 1A, the fifth, sixth, and ninth latches 104e, 104f, and 104i operate at the same phase of the first clock signal. Thus, the fifth and sixth latches 104e and 104f are opaque when the ninth latch 104i is opaque. The ninth latch 104i holds the delayed first feedback signal at a constant logic state, irrespective of the change in logic state of the first feedback signal due to the first clock signal. The purpose of the fifth and sixth latches 104e and 104f for holding the delayed first and second compensated signals is defeated. Similarly, there is redundancy amongst the seventh, eighth, and tenth latches 104g, 104h, and 104j. Therefore, the fifth through eighth latches are eliminated without altering the function of the DFE 100.
However, for the DFE 100 to function accurately, it is important that the first and second clock signals have a 50 percent duty cycle. If the first and second clock signals fail to have a 50 percent duty cycle, the first through fourth latches 104a-104d may have hold issues leading to functional failure. Further, the first through fourth latches 104a-104d are sense amplifier-type latches that are edge triggered. When either of the first or second clock signals transition from a high to a low logic state, the first through fourth latches 104a-104d lose the data bits captured in the analog input signal. The loss of the data bits is undesirable.
Therefore, it would be advantageous to have a DFE that operates at clock signals with multiple duty cycles, does not lose data bits at the transition of logic states of the clock signals, achieves the fundamental timing limit, and overcomes the above-mentioned limitations of conventional DFEs.